/*
 * Copyright (c) 2022 ASPEED Technology Inc.
 *
 * SPDX-License-Identifier: MIT
 */

#pragma once

typedef char byte;

typedef enum _PLATFORM_STATE_VALUE {
	CPLD_NIOS_II_PROCESSOR_WAITING_TO_START = 0X1,
	CPLD_NIOS_II_PROCESSOR_STARTED,
	ENTER_T_MINUS_1,
	BMC_FLASH_AUTH                          = 0X6,
	PCH_FLASH_AUTH,
	LOCKDOWN_ON_AUTH_FAIL,
	ENTER_T0,
	T0_BMC_BOOTED,
	T0_ME_BOOTED,
	T0_ACM_BOOTED,
	T0_BIOS_BOOTED,
	T0_BOOT_COMPLETED,
	PCH_FW_UPDATE           = 0X10,
	BMC_FW_UPDATE,
	CPLD_FW_UPDATE,
	CPLD_FW_UPDATE_IN_RECOVERY_MODE,
#if defined(CONFIG_SEAMLESS_UPDATE)
	PCH_SEAMLESS_UPDATE,
	PCH_SEAMLESS_UPDATE_DONE,
#endif
#if defined(CONFIG_INTEL_PFR_CPLD_UPDATE)
	INTEL_CPLD_STATE_AUTH = 0x16,
	INTEL_CPLD_STATE_BOOTED_CFM_0,
	INTEL_CPLD_STATE_BOOTED_CFM_1_2,
	INTEL_CPLD_STATE_UPDATE,
	INTEL_CPLD_STATE_RECOVERY,
	INTEL_CPLD_STATE_RECOVERY_BOOT_CFM_0,
#endif
	T_MINUS_1_FW_RECOVERY   = 0X40,
	T_MINUS_1_FORCED_ACTIVE_FW_RECOVERY,
	WDT_TIMEOUT_RECOVERY,
	CPLD_RECOVERY_IN_RECOVERY_MODE,
	LOCKDOWN_DUE_TO_PIT_L1,
	PIT_L2_FW_SEALED,
	LOCKDOWN_ON_PIT_L2_PCH_HASH_MISMATCH,
	LOCKDOWN_ON_PIT_L2_BMC_HASH_MISMATCH
} PLATFORM_STATE_VALUE;

typedef enum _LAST_RECOVERY_REASON_VALUE {
	PCH_ACTIVE_FAIL = 0x1,
	PCH_RECOVERY_FAIL,
	ME_LAUNCH_FAIL,
	ACM_LAUNCH_FAIL,
	IBB_LAUNCH_FAIL,
	OBB_LAUNCH_FAIL,
	BMC_ACTIVE_FAIL,
	BMC_RECOVERY_FAIL,
	BMC_LAUNCH_FAIL,
	CPLD_WDT_FAIL,
	FORCED_ACTIVE_RECOVERY
} LAST_RECOVERY_REASON_VALUE;

typedef enum _LAST_PANIC_REASON_VALUE {
	PCH_UPDATE_INTENT = 0x1,
	BMC_UPDATE_INTENT,
	BMC_RESET_DETECT,
	BMC_WDT_EXPIRE,
	ME_WDT_EXPIRE,
	ACM_WDT_EXPIRE,
	IBB_WDT_EXPIRE,
	OBB_WDT_EXPIRE,
	ACM_IBB_0BB_AUTH_FAIL
} LAST_PANIC_REASON_VALUE;

typedef enum _MAJOR_ERROR_CODE_VALUE {
	BMC_AUTH_FAIL = 0x1,
	PCH_AUTH_FAIL,
	FW_UPDATE_FAIL,
	PFR_AUTH_FAIL = 0x04,
#if defined(CONFIG_PFR_SPDM_ATTESTATION)
	ATTESTATION_MEASUREMENT_FAIL = 0x05,
	ATTESTATION_CHALLENGE_FAIL = 0x06,
	SPDM_PROTOCOL_ERROR_FAIL = 0x07,
	SPDM_COMMUNICATION_ERROR_FAIL = 0x08,
#endif
#if defined(CONFIG_INTEL_PFR_CPLD_UPDATE)
	INTEL_CPLD_AUTH_FAIL = 0x09,
	INTEL_CPLD_UPDATE_FAIL = 0x0A,
	INTEL_CPLD_COMMUNICATION_FAIL = 0x0B,
#endif
} MAJOR_ERROR_CODE_VALUE;

typedef enum _MINOR_ERROR_CODE_VALUE {
	// BMC/PCH auth failure
	ACTIVE_AUTH_FAIL                = 0x1,
	RECOVERY_AUTH_FAIL,
	ACTIVE_RECOVERY_AUTH_FAIL,
	ACTIVE_RECOVERY_STAGING_AUTH_FAIL,
	AFM_ACTIVE_AUTH_FAIL,
	AFM_RECOVERY_AUTH_FAIL,
	AFM_ACTIVE_RECOVERY_AUTH_FAIL,
	AFM_ACTIVE_RECOVERY_STAGING_AUTH_FAIL,

	// Firmware/ROT/Seamless update failure
	INVALID_UPD_INTENT              = 0x1,
	UPD_CAPSULE_INVALID_SVN,
	UPD_CAPSULE_AUTH_FAIL,
	UPD_EXCEED_MAX_FAIL_ATTEMPT,
	UPD_NOT_ALLOWED,
	UPD_CAPSULE_TO_RECOVERY_AUTH_FAIL,
	AFM_UPD_NOT_ALLOWED,
	AFM_UNKNOWN_AFM,
#if defined(CONFIG_SEAMLESS_UPDATE)
	SEAMLESS_UNKNOWN_FV_TYPE        = 0x10,
	SEAMLESS_AUTH_FAILED_AFTER_UPDATE,
#endif

#if defined(CONFIG_INTEL_PFR_CPLD_UPDATE)
	INTEL_CPLD_IMAGE_AUTH_FAIL            = 0x12,
	INTEL_CPLD_IMAGE_TOCTOU,
	INTEL_CPLD_IMAGE_SUPPORT_MODE,
	INTEL_CPLD_IMAGE_SCM_CPLD,
	INTEL_CPLD_IMAGE_CPU_CPLD,
	INTEL_CPLD_IMAGE_DEBUG_CPLD,
	INTEL_CPLD_IMAGE_LOAD_IMAGE,
	INTEL_CPLD_IMAGE_RECOVERY_AUTH_FAIL,
#endif

#if defined(CONFIG_PFR_SPDM_ATTESTATION)
	// Attestation failure
	SPDM_CONNECTION_FAIL            = 0x01,
	SPDM_DIGEST_FAIL                = 0x02,
	SPDM_CERTIFICATE_FAIL           = 0x03,
	SPDM_CHALLENGE_FAIL             = 0x04,
	SPDM_MEASUREMENT_FAIL           = 0x05
#endif
} MINOR_ERROR_CODE_VALUE;

typedef enum _UFM_PROVISONING_STATUS_VALUE {
	COMMAND_BUSY                    = 0X1,
	COMMAND_DONE                    = 0X2,
	COMMAND_ERROR                   = 0X4,
	UFM_LOCKED                      = 0X10,
	UFM_PROVISIONED                 = 0X20,
	PIT_LEVEL_1_ENFORCED            = 0X40,
	PIT_L2_COMPLETE_SUCCESSFUL      = 0X80,
	UFM_CLEAR_ON_NEW_COMMAND       = COMMAND_BUSY | COMMAND_DONE | COMMAND_ERROR,
   	UFM_CLEAR_ON_ERASE_COMMAND     = UFM_PROVISIONED | PIT_LEVEL_1_ENFORCED | PIT_L2_COMPLETE_SUCCESSFUL,
} UFM_PROVISONING_STATUS_VALUE;

typedef enum _UFM_PROVISIONING_COMMAND_VALUE {
	ERASE_CURRENT           = 0,
	PROVISION_ROOT_KEY,
	PROVISION_PIT_KEY,
	PROVISION_PCH_OFFSET    = 0X5,
	PROVISION_BMC_OFFSET,
	LOCK_UFM,
	READ_ROOT_KEY,
	PROVISION_AFM_OFFSET    = 0x9,
	READ_AFM_OFFSET         = 0xa,
	READ_PCH_OFFSET         = 0xc,
	READ_BMC_OFFSET,
	RECONFIG_CPLD,
	ENABLE_PIT_LEVEL_1_PROTECTION = 0X10,
	ENABLE_PIT_LEVEL_2_PROTECTION,
	ENABLE_DEVICE_ATTESTATION_REQUESTS = 0X12,
	READ_DEVICE_ID_PUBLIC_KEY = 0X13,
	DISABLE_DEVICE_ATTESTATION_REQUESTS = 0X14,
} UFM_PROVISIONING_COMMAND_VALUE;

typedef enum _UFM_COMMAND_TRIGGER_VALUE {
	EXECUTE_UFM_COMMAND     = 0X1,
	FLUSH_WRITE_FIFO        = 0X2,
	FLUSH_READ_FIFO         = 0X4
} UFM_COMMAND_TRIGGER_VALUE;

typedef enum _BMC_CHECKPOINTS_VALUE {
	STARTED_EXECUTION_BLOCK = 1,
	NEXT_EXECUTION_BLOCK_AUTH_PASS,
	NEXT_EXECUTION_BLOCK_AUTH_FAIL,
	EXIT_PLATFORM_MANUFACTURER_AUTHORITY,
	STARTED_EXTERNAL_EXECUTION_BLOCK,
	RETURNED_FROM_EXTERNAL_EXECUTION_BLOCK,
	PAUSEING_EXECUTION_BLOCK,
	RESUMING_EXECUTION_BLOCK,
	COMPLETING_EXECUTION_BLOCK,
	ENTERED_MANAGEMENT_MODE,
	lEAVING_MANAGEMENT_MODE,
	HOST_READY_TO_BOOT = 0X80,
	HOST_EXIT_BOOT_SERVICES,
	RESET_HOST,
	RESET_ME,
	RESET_BMC
} BMC_CHECKPOINTS_VALUE;

typedef enum _ACM_BIOS_CHECKPOINT_VALUE {
	EXECUTION_BLOCK_STARTED = 1,
	AUTHENTICATION_FAILED   = 3,
	EXECUTION_BLOCK_PAUSED  = 7,
	EXECUTION_BLOCK_RESUMED,
	EXECUTION_BLOCK_COMPLETED
} ACM_BIOS_CHECKPOINT_VALUE;

typedef enum _BMC_PCH_UPDATE_INTENT_VALUE {
	PCH_ACTIVE      = 0X1,
	PCH_RECOVERY    = 0X2,
	CPLD_ACTIVE     = 0X4,
	BMC_ACTIVE      = 0X8,
	BMC_RECOVERY    = 0X10,
	CPLD_RECOVERY   = 0X20,
	UPDATE_DYNAMIC  = 0X40,
	UPDATE_AT_RESET = 0X80
} BMC_PCH_UPDATE_INTENT_VALUE;

typedef enum _PFR_ACTIVITY_STATUS_1_VALUE {
	PFR_ACT1_DAA_I3C_BMC                = 0b1,
	PFR_ACT1_SET_EID_I3C_BMC            = 0b10,
	PFR_ACT1_EID_REGISTRATION_I3C_BMC   = 0b100,
	PFR_ACT1_I3C_MUX_TAKEOVER           = 0b1000,
	PFR_ACT1_DAA_I3C_CPU                = 0b10000,
	PFR_ACT1_SET_EID_I3C_CPU            = 0b100000,
	PFR_ACT1_EID_REGISTRATION_I3C_CPU   = 0b1000000,
} PFR_ACTIVITY_STATUS_1_VALUE;

typedef enum _PFR_ACTIVITY_STATUS_2_VALUE {
	PFR_ACT2_BMC_BOOT_DONE              = 0b1,
	PFR_ACT2_IBB_BOOT_DONE              = 0b10,
	PFR_ACT2_OBB_BOOT_DONE              = 0b100,
} PFR_ACTIVITY_STATUS_2_VALUE;

